1. Field
This disclosure relates generally to clock generators, and more particularly to clock generators that generate a clock that has a frequency double that of an input clock.
2. Related Art
Many integrated circuits have operations that require a clock and utilize a master clock to generate the various clocks as needed. One clock that is often beneficial is one that is double that of the master clock. One example is an analog to digital converter where a desired sample rate is greater than that of the master clock or twice as many phases are required from the master clock to perform the conversion and doubling is commonly what is desired. A frequency doubler typically is preferred to have a 50 percent duty cycle, and it is also preferred that the doubler have a comparatively fast start-up time. Although phase locked loops are effective at achieving the desired 50 percent duty cycle, the fast start-up time is difficult to achieve. Other methods such as variable delays with XOR gates to double the clock frequency take time to stabilize to the desired 50% duty cycle.
Accordingly there is a need to provide further improvement in achieving a frequency doubler.